This application relies for priority upon Korean Patent Application No. 2001-15161, filed on Mar. 23, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to the field of a phase locked loop (PLL) circuit, and more particularly to a PLL circuit for a fractional-N frequency synthesizer.
FIG. 1 is a circuit diagram showing a configuration of a conventional phase locked loop (PLL) circuit having an integer frequency divider. Referring to FIG. 1, a phase-frequency comparator 10 receives a reference signal (i.e. input signal) Fin and a feedback signal Ffeed, which is obtained by dividing an output signal Fout of a voltage controlled oscillator (VCO) 40 by a frequency divider 50. The phase-frequency comparator 10 detects a phase error between the Fin and Ffeed, and outputs pulse signals UP and DN corresponding to the phase error. A charge pump 20 generates a charge pump output current Icp in response to the pulse signals UP and DN. The charge pump output current Icp flows to a loop filter 30. The loop filter 30 removes a high frequency constituent of the Icp, and outputs a control voltage Vctrl in proportion to the inputted current Icp. The VCO 40 generates the output signal Fout in proportion to the control voltage Vctrl of the loop filter 30. The output signal of the VCO 40 is divided by N, that is, multiplied by 1/N, by the frequency divider 50, and is fed back to the phase-frequency comparator 10 as the feedback signal Ffeed. Accordingly, the output signal Fout of the VCO 40 can be described by the following equation (1).
Fout=Nxc3x97Finxe2x80x83xe2x80x83(1) 
Here, a division ratio N of the frequency divider 50 is a positive integer. Therefore, the PLL circuit can obtain the output signal Fout having a frequency that are N times higher than that of the reference signal Fin. For the reason, the frequency of the output signal Fout can be divided by the integer N.
In the PLL circuit, it is possible to raise the frequency of the Fin or to increase the division ratio N for improving the circuit""s capacity for locking phases. If the frequency of the Fin is raised in order to improve the capacity of locking phases, the frequency interval of Fout is also increased. In a communication unit, an increase of the frequency interval of the signal Fout can cause a corresponding decrease in the number of usable frequency bands.
In order to maintain the frequency of the output signal, while, at the same time, lowering the frequency of the reference signal, it is necessary to increase the division ratio N. However, a high division ratio causes an increase in phase noise by drawing the loop band close to the carrier frequency. Generally, the phase noise increases along the dimension of log scale of the division ratio (about 20 logN).
In order to solve the above problem, a fractional-N frequency PLL circuit is proposed in the present invention. In the fractional-N frequency PLL circuit, the frequency interval of the output signal Fout is smaller than that of the reference signal Fin.
For example, in the PLL circuit, in the case that among the total number of division K, the input signal or the reference signal is divided by division ratio N+1 in F times, and is divided by division ratio N in Kxe2x88x92F times, an average frequency of signal outputted from the VCO can be described by the following equation (2).                               F          out                =                                                            (                                  F                  xc3x97                                      (                                          N                      +                      1                                        )                                                  )                            +                              (                                                      (                                          K                      -                      F                                        )                                    xc3x97                  N                                )                                      K                    =                      N            +                          F              N                                                          (        2        )            
That is, it is possible to be divided by not only N but also F/K. The output signal Fout converges on an average value through the loop filter 30 composing a resistor 31 and a capacitor 32, and thereby a fractional division can be performed.
The fractional-N frequency PLL circuit can be embodied by using a phase accumulating circuit having a compensating circuit, a sigma delta modulator, phase interpolation, and the like.
The fractional-N frequency PLL circuit using a phase accumulating method is limited by phase that accumulates in an accumulator. This, in turn, causes increase in spurious noise or fractional noise as much as the accumulated phase. In order to solve this problem, the bandwidth of the system can be reduced. However, in this case, there is no need for the fractional-N frequency synthesizer to be used. Therefore, the frequency synthesizer has been developed to employ a circuit for compensating for spurious noise or a spurious signal cancellation circuit. This concept is proposed in U.S. Pat. No. 5,818,303 xe2x80x9cFractional N-frequency Synthesizer and Spurious Signal Cancel Circuitxe2x80x9d. Since the phase accumulating circuit requires the additional compensation circuit, the size of the circuit is therefore increased.
A noise regulating method used in the high order sigma-delta modulator is able to suppress fractional spurious signals. An example of the noise regulating method is proposed in xe2x80x9cA Multiple Modulator Fractional Dividerxe2x80x9d (B. Miller and R. J. Conley, IEEE Transactions on Instrumentation and Measurement. Vol. 40, pp. 578-583, June 1991). The proposed noise regulating method decreases a phase error from a phase-frequency comparator, resulting in eliminating the phase error of low frequencies by rapidly switching different division ratios. However, in this case, it is possible to generate a phase error in not only a negative pole but also in a positive pole.
The method of the phase interpolation causes the VCO output signal to be a plurality of signals with the same delay time and different phases, and divides the signals using each delay time. However, since each delay time should be identical, a delicate arrangement technology is required for the phase interpolation method. Further, the resulting increase in the number of output signals causes a corresponding increase in substrate noise and noise generated by physical conditions.
The object of the present invention is to provide an improved phase locked loop (PLL) circuit for a fractional-N frequency synthesizer so as to address the limitations of conventional approaches.
According to an aspect of the present invention, the PLL circuit for a fractional frequency division synthesizer includes a voltage controlled oscillator (VCO) for generating an output signal of a frequency in proportion to a predetermined frequency control voltage, and for generating a clock signal delayed by a time period corresponding to fractional division control data, an integer division logic circuit for generating a feedback signal by dividing a is delayed clock signal supplied from the VCO in response to an integer division ratio data from external sources and a predetermined division ratio, a phase comparator for detecting a phase error between an input signal and the feedback signal, and for generating a phase error signal corresponding to the phase error, a charge pump circuit for generating a charge pump output current corresponding to the phase error signal, and a loop filter for converting the charge pump output current to the frequency control voltage.
The delayed clock signal generated y the VCO may comprise a fractional divided clock signal.
The VCO may include an oscillator for an output signal of frequency in proportion to the frequency control voltage, and for generating delay signals of 2Y numbers (Y is a positive integer) delayed a predetermined time comparing with the output signal, and a switching circuit for generating the delayed clock signal from one of the 2Y delay signals in response to the fractional division control data.
In a preferred embodiment, each delay signal has a similar delay time, and the sum of delay times of each delay signal is equal to a cycle of the output signal. Further, only one of said 2Y fractional division control data bits has a value of logic xe2x80x981xe2x80x99 exclusively.
The switching circuit is composed of 2Y switches respectively corresponding to the delay signals generated from the oscillator, where each switch is controlled by the corresponding fractional division control data bit, and transfers the delay signal generated from the oscillator to the delayed clock signal.
The fractional division ratio data is composed of X-bits (X is a positive integer). The fractional division control logic circuit includes a second counter, a third counter, a decoder, and a latch circuit, where the second counter performs counting operations in synchronously response to the feedback signal and compares an internal count value with a high-order bit (X-Y) of the fractional division ratio data, resulting in generating a second control signal, the third counter performs counting operations during time corresponding to a value adding the second control signal to a low-order bit of the fractional division ratio data, and thereby generating a count value, the decoder generates a decoding data from the count value of the third counter, and the latch circuit generates in synchronous response to the delayed clock signal the fractional division control data from the decoding data.
The second counter generates the second control signal of logic xe2x80x981xe2x80x99 if the internal count value is lower than the high-order bit (X-Y) of the fractional division ratio data, and generates the second control signal of logic xe2x80x980xe2x80x99 if the internal count value is equal to or greater than the high-order bit (X-Y).
The integer division logic circuit includes a dual modulus prescaler, a frequency divider, and a first counter, where the dual modulus prescaler selects one of predetermined plural division ratios in response to a first control signal, and divides the clock signal divided by the selected division ratio, resulting in generating a first division signal, the frequency divider divides the first division signal in response to the integer division ratio data, and generates the feedback signal, and the first counter performs counting operations in synchronously response to the feedback signal, and compares the internal count value with a critical value supplied from external sources, resulting in generating the first control signal.
The first counter generates the first control signal having logic xe2x80x981xe2x80x99 if the internal count value is lower than the critical value supplied from external sources, and generates the first control signal having logic xe2x80x980xe2x80x99 if the internal count value is equal to or greater than the critical value.
Further, the first counter may be formed of a swallow counter.